In high-end ICE systems, two processors are generally employed. One processor controls the system and interacts with the user, while the other processor (similar or identical to a device being emulated) runs the user code to emulate the operation of the device being emulated.
In low-cost ICE systems, however, only a single processor may be available to run both the control code as well as the user code. If the processor has a large address space, then both the control code and the user code may concurrently be addressable within its memory address map with minimal impact on the ICE system's target environment (i.e., without unduly limiting the size of the user code or the amount of code for controlling the system and interacting with the user). On the other hand, if the processor has a small address space, then the size of the user code and/or control code may be adversely limited by concurrent inclusion of the control code in the processor's memory address map, thus adversely impacting the ICE system's target environment.